Micro Electronics Engineer

Job ID: TEC-EDP-909A

Deadline: 06 February 2023

Aurora is an established supplier of skilled manpower to ESA and in particular at ESTEC and ESAC. Aurora has the opportunity to expand our support to ESA in the domain of TEC-EDP – Electromagnetics Components Data & Power Systems Engineering, supporting the Microelectronics Section.
Happiness of our employees has proven key to obtaining excellent results and a client who also regards us highly for excellent service.


Provision of VLSI (ASIC & FPGA) technical expertise to Projects involving requirements analysis, performance and budgets analysis, writing and assessment of VLSI specifications; review, evaluation and checking of industrial contractor’s VLSI designs. Identification of design deficiencies and problem areas and proposals for their solutions.

Design, analysis, verification of VLSI systems for control and data processing applications, and/or signal processing using industrial standard tools, hardware description and programming languages.

Specific Requirements/tasks

  • Technical and administrative management of the ESA SystemC and synthesizable VHDL IP Core pool of designs. This work will involve: optimisation, update and overall maintenance and of the ESA VHDL IP Cores databases, provision of technical support to ESA IP Cores users (performing analysis and finding solutions to problems in VHDL code, documentation or design methodology) holding a strong collaboration with our Contracts department in arranging and solving licences and patent issues. Advertising the ESA IP service (website, workshops, etc.), handling IP cores requests and their distribution.
  • The post holder will support ASIC and/or FPGA technology developments for R&D and /or projects, supervising that good design practices and manufacturing and test methodologies are applied. In addition, independent verification (through code inspection, simulation and timing analysis) and validation (through HW tests) will have to be carried out for some ASIC and FPGAS developments.
  • Support development contracts regarding the above areas, act as the activity technical responsible, maintain interfaces with the prime contractors, participate in progress meetings and reviews, as requested, and provide appropriate feedback on the achieved progress and discussions.
  • When supporting projects, interface with ESA’s project teams, the prime and lower level contractors, participate in progress meetings and reviews, as requested by project work, and provide appropriate feedback on the achieved progress and discussions.

Specific qualification requirements

  • Master’s degree in Electronics Engineering or Physics, specialized in digital signal processing and microelectronics, with five or more years of experience in at least three of the following domains:-
  • Development of digital signal processing architecture, simulation, implementation and validation, including the coding into a hardware description language (HDL).
  • Development of functional and performance test cases and benches for the verification, profiling and validation of the digital signal processing architecture.
  • Design and test of digital FPGAs and ASICs (specifications, block design, top level integration, design for test, pre and post layout simulation and timing analysis, gates synthesis, support during layout, prototype test and in system validation), with proficiency in HDL (VHDL, Verilog and System-C).
  • VLSI IC Design CAD tools such as: Synopsys, CADENCE, Mentor, MATLAB and/or Simulink as well as hardware description languages (VHDL, Verilog, SystemVerilog, SystemC, …).
  • FPGA HW and SW of several vendors such as: Xilinx, Microchip (former Microsemi, former ACTEL) and/or NanoXplore.
  • Preparation of digital FPGA and ASIC design test-benches, for functional verification, validation and electrical characterization, using signal generators, oscilloscopes and signal analyzers.
  • System administration in UNIX and Windows for IC Design CAD tools.

Important additional assets would be:

  • Strong foundations in mathematics, linear algebra, physics and signal processing intuition regarding time/frequency duality, implications of discrete time signal processing, and implementation details on fixed/floating point architectures.
  • Knowledge of space wireless and wireline communications systems, standards, including physical, data link, network and transport layer design for Spacewire, SpaceFibre, CAN, PCIe, JESD204B/C, Ethernet, IEEE 802.15(a).
  • Knowledge of encoding and decoding, forward error correction (FEC) blocks, interleaving, digital pre-distortion, modulation and demodulation (PSK, PAM, QAM, OFDM, etc), spreading and despreading, encryption and decryption and link budget.
  • Knowledge of converters, baseband sampling, direct digital conversion, digital filters, fast fourier transforms, feature extraction, estimation, decision-making, detection, acquisition, tracking and adaptive control.
  • Knowledge of standard interfaces architectures: Spacewire, SpaceFibre, PCIe, Ethernet, JESD204B/C, SerDes (NRZ, PAM4), AMBA, AXI, DDR, etc.
  • Experience in developing automated, self-checking test benches, UVM and/or UVVM.
  • Experience with Microprocessors (e.g. SPARC, ARM, RISC-V) and HW-SW co-design.
  • Experience with mitigation of radiation effects and/or radiation tests of FPGAs and/or ASICs.
  • Knowledge of the Space environment, its effects on microelectronics devices and related technology, as well as ECSS quality standards applied to space VLSI ICs.
  •  Experience with using third party Intellectual Property (IP) designs (in VHDL and/or SystemC) is a requirement.
  • The candidate should have good inter-personal communication skills and high motivation to work in a multi disciplinary and international environment with confidence and autonomy.
  • A good knowledge of English is required. Knowledge of another member state language is considered an asset.
  • Fluency in English (both written and spoken) is mandatory; knowledge of another European language is an advantage.

NOTE: for candidates with less than 10 years experience, the relevant academic transcripts must be provided in order to give a more complete candidate profile at the selection stage.

Legal and Security Requirements

  • All applicants must be legally allowed to work in The Netherlands
  • Applicants are required to provide a copy of their passport and degree certificate. Aurora will validate the Degree with the issuing University and provide evidence to ESA.
  • Prior to issuing a letter of employment the applicant shall provide to Aurora a recent official document declaring that they are of good conduct from the country where currently resident.


The work will be performed at the European Space Technology and Research Centre (ESTEC) at Noordwijk, The Netherlands.


  • The selected candidate will receive good remuneration  in line with ESA Job Class.
  • Will be registered for both social security and tax in the Netherlands.
  • The standard working hours are 40 per week. There are 12 public holidays and an additional 30 annual days holiday.
  • Training to improve efficiency and provide strength for future career are of course included.
  • Aurora assists with relocation both with support and financially.
  • Aurora contributes to a company pension scheme.

To be considered  apply for this Position

Prior to 06 February 2023, please apply via our Job Application form quoting TEC-EDP-909A (RT-C/TEC-EDM/00909A) as reference.

Aurora will agree conditional employment terms and conditions with candidates before presenting them by 07 February 2023, 13.00 hours.

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